View LTC3622-23-15_8980697.PDF datasheet online --- IC-ON-LINE

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1 for more information www.linear.com/ltc3622 typical a pplica t ion fea t ures descrip t ion 17v, dual 1a synchronous step-down regulator with ultralow quiescent curr ent the lt c ? 3622 is a dual 1 a output, high efficiency synchro- nous monolithic step-down regulator capable of operating from input supplies up to 17 v. the switching frequency is fixed to 1 mhz or 2.25 mhz with a 50% synchronization range to an external clock. the regulator features ultralow quiescent current and high efficiency over a wide output voltage range. the step-down regulators operate from an input voltage range of 2.7 v to 17 v and provide an adjustable output from 0.6 v to v in while delivering up to 1 a of output cur- rent. a user-selectable mode input is provided to allow the user to trade off ripple noise for light load efficiency. burst mode ? operation provides the highest efficiency at light loads, while pulse- skipping mode provides the lowest ripple noise. the switching regulators can be synchronized to an external clock. furthermore, fixed v out options are available to eliminate the external feedback resistors. 2.5v/5v v out application, f sw = 1mhz efficiency vs load current a pplica t ions n dual step-down outputs: 1a per channel n wide v in range: 2.7v to 17v n wide v out range: 0.6v to v in n up to 95% efficiency n no-load i q = 5a with both channels enabled; i q < 4a with only one channel enabled n high efficiency, low dropout operation (100% duty cycle) n constant frequency (1mhz/2.25mhz) with external frequency synchronization n 1% output voltage accuracy n current mode operation for excellent line and load transient response n phase shift programmable with external clock n selectable current limit n internal compensation and soft-start n compact 14-pin dfn (3mm 4mm) and 16-lead msop packages n battery powered systems n point-of-load supplies n portable C handheld scanners l, lt , lt c , lt m , burst mode, linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6580258, 6498466, 6611131, 5705919. list of ltc3622 options part name frequency v out ltc3622 1.00mhz adjustable ltc3622-2 2.25mhz adjustable ltc3622-23/5 2.25mhz 5v/3.3v load current (a) efficiency (%) power loss (w) 3622 ta01b 90 80 100 70 60 50 40 30 20 10 0 0.5 0.4 0.6 0.3 0.2 0.1 0 0.0001 0.001 0.01 0.1 1 v out2 = 5v v out1 = 2.5v v in = 12v f sw = 1mhz burst mode operation 22pf 619k 84.5k 6.8h 4.7h 3622 ta01 run1 run2 gnd fb1 sw1 v in1 v in 5.5v to 17v v out2 5v 1a c out2 22f c in 10f c1 1f v in2 phase i lim intv cc mode/sync sw2 fb2 ltc3622 22pf 619k 196k v out1 2.5v 1a c out1 22f ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
2 for more information www.linear.com/ltc3622 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in 1 , v in 2, sv in ( msop only ) ( note 2) ....... C 0.3 v to 17 v run 1, run 2 .............................................. C 0.3 v to 17 v mode / sync , fb 1, fb 2 ................................ C 0.3 v to 6v pgood 1, pgood2, i lim , phase .................. C 0.3 v to 6v (note 1) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 sw1 run1 fb1 intv cc fb2 run2 sw2 v in1 pgood1 mode/sync phase pgood2 i lim v in2 top view de package 14-lead (4mm 3mm) plastic dfn 15 gnd t jmax = 150c, ja = 40c/w, jc = 4.4c/w exposed pad ( pin 15) is gnd, must be soldered to pcb 1 2 3 4 5 6 7 8 v in1 sv in pgood1 mode/sync phase pgood2 i lim v in2 16 15 14 13 12 11 10 9 sw1 nc run1 fb1 intv cc fb2 run2 sw2 top view mse package 16-lead plastic mse 17 gnd t jmax = 150c, ja = 40c/w, jc = 10c/w exposed pad ( pin 17) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3622ede#pbf ltc3622ede#trpbf 3622 14-lead (3mm x 4mm) plastic dfn C40c to 125c ltc3622ide#pbf ltc3622ide#trpbf 3622 14-lead (3mm x 4mm) plastic dfn C40c to 125c ltc3622hde#pbf ltc3622hde#trpbf 3622 14-lead (3mm x 4mm) plastic dfn C40c to 150c ltc3622emse#pbf ltc3622emse#trpbf 3622 16-lead plastic msop C40c to 125c ltc3622imse#pbf ltc3622imse#trpbf 3622 16-lead plastic msop C40c to 125c ltc3622hmse#pbf ltc3622hmse#trpbf 3622 16-lead plastic msop C40c to 150c ltc3622ede-2#pbf ltc3622ede-2#trpbf 36222 14-lead (3mm x 4mm) plastic dfn C40c to 125c ltc3622ide-2#pbf ltc3622ide-2#trpbf 36222 14-lead (3mm x 4mm) plastic dfn C40c to 125c ltc3622hde-2#pbf ltc3622hde-2#trpbf 36222 14-lead (3mm x 4mm) plastic dfn C40c to 150c ltc3622emse-2#pbf ltc3622emse-2#trpbf 36222 16-lead plastic msop C40c to 125c ltc3622imse-2#pbf ltc3622imse-2#trpbf 36222 16-lead plastic msop C40c to 125c ltc3622hmse-2#pbf ltc3622hmse-2#trpbf 36222 16-lead plastic msop C40c to 150c ltc3622ede-23/5#pbf ltc3622ede-23/5#trpbf 223/5 14-lead (3mm x 4mm) plastic dfn C40c to 125c ltc3622ide-23/5#pbf ltc3622ide-23/5#trpbf 223/5 14-lead (3mm x 4mm) plastic dfn C40c to 125c ltc3622hde-23/5#pbf ltc3622hde-23/5#trpbf 223/5 14- lead (3mm x 4mm) plastic dfn C40c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating junction temperature range ( note 3) ltc 36 22 e .......................................... C4 0 c to 125 c ltc 36 22 i ........................................... C4 0 c to 125 c ltc 36 22 h .......................................... C 40 c to 150 c storage temperature range .................. C 65 c to 150 c ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
3 for more information www.linear.com/ltc3622 symbol parameter conditions min typ max units v in1 , v in2 operating voltage 2.7 17 v sv in operating voltage msop package 2.7 17 v v out operating voltage 0.6 v in v i q input quiescent current active mode, v run1 = v run2 = 2v (note 4) burst mode operation, v run1 = v run2 = 2 v, mode/ sync = 3v , no load shutdown mode; v run1 = v run2 = 0v 3 5 0.1 10 1 ma a a v fb regulated feedback voltage ltc3622/ltc3622-2 l 0.594 0.591 0.6 0.6 0.606 0.609 v i fb fb input current ltc3622/ltc3622-2 10 na v out1 regulated fixed output voltage (channel 1) ltc 3622-23/5 l 4.950 4.925 5.0 5.0 5.050 5.075 v v v out2 regulated fixed output voltage (channel 2) ltc 3622-23/5 l 3.267 3.250 3.3 3.3 3.333 3.350 v v i fb(vout) feedback input leakage current ltc3622-23/5 1 5 a reference voltage line regulation v in = 2.7v to 17v (note 5) 0.01 0.015 %/v output voltage load regulation (note 5) 0.1 % nmos switch leakage pmos switch leakage 0.1 0.1 1 1 a a r ds(on) nmos on-resistance pmos on-resistance v in = 5v 0.15 0.37 maximum duty cycle v fb = 0v l 100 % t on(min) minimum on-time v fb = 0.7v, v in1 = v in2 = 5 75 ns v run run input high run input low 0.35 1.0 v v run input current v run = 12v 0.1 20 na v mode pulse-skipping mode burst mode operation v intvcc C0.4 0.15 v v phase input threshold input low input high 2.0 0.4 v v i lim input threshold input low input high v intvcc C0.1 0.1 intv cc v v t ss soft start time 0.5 ms i lim peak current limit v in > 5v v ilim = 0.1v (both channels) v ilim = intv cc C 0.1v (both channels) v ilim = floating, channel 1 v ilim = floating, channel 2 1.6 0.8 1.6 0.8 1.8 1.0 1.8 1.0 2.0 1.2 2.0 1.2 a a a a v intvcc undervoltage lockout v in ramping up 2.3 2.5 2.65 v v intvcc undervoltage lockout hysteresis 160 mv v in overvoltage lockout rising l 18 19 20 v v in overvoltage lockout hysteresis 300 mv e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in1 = v in2 = 12v, unless otherwise noted. (notes 3, 6) ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
4 for more information www.linear.com/ltc3622 the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in1 = v in2 = 12v, unless otherwise noted. (notes 3, 6) e lec t rical c harac t eris t ics symbol parameter conditions min typ max units f osc oscillator frequency ltc3622-2/ltc3622-23/5 C40c t a 150c ltc3622 C40c t a 125c ltc3622 C40c t a 150c l l l 1.8 0.82 0.75 2.25 1.00 1.00 2.6 1.16 1.16 mhz mhz mhz external clk amplitude 0.4 v intvcc C0.3 v sync capture range % of programmed frequency 50 150 % v intvcc intv cc voltage 3.3 3.6 3.9 v power good range v in > 4v C7.5 C11 % r pgood power good resistance pgood r ds(on) at 2ma 275 350 t pgood pgood delay pgood low to high pgood high to low 0 32 cycles cycles phase shift between channel 1 and channel 2 v phase = 0v v phase = intv cc , v mode/sync = 0v 0 180 deg deg note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. transient absolute maximum voltages should not be applied for more than 4% of the switching duty cycle. note 3. the ltc3622 is tested under pulsed load conditions such that t j t a . the ltc3622e is guaranteed to meet specified performance from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3622i is guaranteed over the C40 c to 125c operating junction temperature range and the ltc3622h is guaranteed over the -40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environment factors. note 4. the quiescent current in active mode does not include switching loss of the power fets. note 5. the ltc3622 is tested in a proprietary test mode that connects v fb to the output of error amplifier. note 6. t j is calculated from the ambient t a and power dissipation p d according to the following formula: t j = t a + (p d ? ja ) ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
5 for more information www.linear.com/ltc3622 burst mode operation pulse-skipping mode operation efficiency vs input voltage efficiency vs load current efficiency vs load current at dropout operation i q vs v in typical p er f or m ance c harac t eris t ics v in1 = v in2 = 12v , t a = 25c , unless otherwise noted. efficiency vs load current v out efficiency vs input voltage above and below dropout efficiency vs load current input voltage (v) efficiency (%) 3622 g04 48 96 36 24 12 84 72 60 0 2.5 4.5 6.5 8.5 18.5 10.5 12.5 14.5 16.5 i load = 1ma i load = 100a i load = 10ma v out = 4.25v f sw = 1mhz burst mode operation load current (a) efficiency (%) 3622 g05 50 90 40 30 10 20 80 70 60 0 0.001 0.01 0.1 1 v in = 12v v out = 1.8v f sw = 1mhz burst mode operation input voltage (v) i q (a) 3622 g07 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 18 i q shut down i q burst mode sw 10v/div il 200ma/div v out ac-coupled 50mv/div 3622 g08 v in = 12v v out = 2.5v burst mode operation i out = 75ma 4s/div sw 10v/div i l 100ma/div v out ac-coupled 20mv/div 3622 g09 v in = 12v v out = 2.5v pulse-skipping mode i out = 10ma 4s/div input voltage (v) efficiency (%) 3622 g06 90 95 85 80 75 70 0 42 6 108 1412 1816 1a load 10ma load v out = 2.5v f sw = 1mhz burst mode operation load current (a) efficiency (%) 3622 g01 90 80 100 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 v out = 5v v out = 2.5v f sw = 1mhz burst mode operation v in = 12v load current (a) efficiency (%) 3622 g02 90 80 100 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 pulse skip burst mode 100% duty cycle f sw = 2.25mhz v in = 5v load current (a) efficiency (%) 3622 g03 90 80 100 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 v out = 3.3v v out = 2.5v v in = 12v f sw = 2.25mhz burst mode operation ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
6 for more information www.linear.com/ltc3622 typical p er f or m ance c harac t eris t ics load step start-up operation oscillator frequency vs temperature v in1 = v in2 = 12v , t a = 25c , unless otherwise noted. oscillator frequency vs supply voltage reference voltage vs temperature r ds(on) vs input voltage r ds(on) vs temperature load regulation line regulation i l 500ma/div v out ac-coupled 200mv/div 3622 g10 v in = 12v v out = 3.3v burst mode operation load step from 100ma to 1a 40s/div i l 200ma/div run 5v/div pgood 2v/div v out 1v/div 3622 g11 50s/div temperature (c) oscillator frequency (khz) 3622 g12 1400 1300 1200 1500 1100 1000 900 800 700 600 500 ?100 ?50 0 10050 150 200 f sw = 1mhz v in = 12v input voltage (v) oscillator frequency (mhz) 3622 g13 2.45 2.40 2.35 2.50 2.30 2.25 2.20 2.15 2.10 2.05 2.00 0 2 4 86 10 12 14 16 18 temperature (c) reference voltage (mv) 3622 g14 600.0 599.5 600.5 599.0 598.5 598.0 597.0 597.5 ?50 503010?10?30 1109070 130 150 input voltage (v) r ds(on) (m) 3622 g15 600 500 400 300 200 100 0 2 4 6 8 10 12 14 16 18 nmos ch2 r ds(on) nmos ch1 r ds(on) pmos ch2 r ds(on) pmos ch1 r ds(on) input voltage (v) r ds(on) (m) 3622 g16 700 600 500 400 300 200 100 ?50 50250?25 15012510075 nmos channel 2 nmos channel 1 pmos channel 2 pmos channel 1 load current (a) ?v out (%) 3622 g17 3 2 5 4 1 0 ?1 ?2 ?3 ?4 ?5 0 0.40.2 0.80.6 1.21.0 burst mode pulse skip v in = 12v v out = 3.3v pulse skipping operation f sw = 1mhz input voltage (v) ?v out (%) 3622 g18 0.3 0.2 0.5 0.4 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 0 63 129 1815 v out = 2.5v i load = 500ma f sw = 1mhz pulse-skipping operation ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
7 for more information www.linear.com/ltc3622 typical p er f or m ance c harac t eris t ics v out vs load current sync mode out-of-phase operation out-of-phase operation v in1 = v in2 = 12v , t a = 25c , unless otherwise noted. i lim vs input voltage i q vs temperature switch leakage vs temperature temperature (c) quiescent current (a) 3622 g19 10 12 14 8 16 6 4 2 0 ?100 0?50 10050 150 200 shutdown sleep temperature (c) sw leakage (na) 3622 g20 50000 30000 35000 40000 45000 25000 20000 15000 10000 5000 0 ?5000 ?50 ?25 0 25 50 75 100 125 150 pmos2 pmos1 nmos2 nmos1 load current (a) v out (v) 3622 g21 4 5 3 2 1 0 0 0.5 1 1.5 2 i lim = intv cc i lim = gnd sw1 10v/div sw2 10v/div 3622 g22 v in = 12v v out = 2.5v, v out = 3.3v l1 = 4.7h, l2 = 3.3h out-of-phase operation 200ns/div external clock 2v/div sw1 10v/div sw2 10v/div 3622 g23 sync mode operation external clock pulse width controls phase shift 200ns/div input voltage (v) i lim (a) 3622 g24 1.0 2.0 0.8 0.6 0.2 0.4 1.6 1.8 1.4 1.2 0 0 3 15 18 96 12 t a = 150c t a = 25c t a = ?45c ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
8 for more information www.linear.com/ltc3622 p in func t ions vin1 (pin 1/pin 1): input voltage of channel 1 step-down regulator. this input also powers the intv cc ldo. pgood1 (pin 2/pin 3): open drain power good indicator for channel 1. mode/ sync ( pin 3/pin 4): burst mode select and external clock synchronization of the step-down regulator. tie mode/sync to intv cc for burst mode operation with a 400ma peak current clamp. tie mode/sync to gnd for pulse- skipping operation. furthermore, connecting this pin to an external clock will synchronize the switch clock to the external clock and put the part in pulse-skipping mode. phase (pin 4/pin 5): phase select pin. tie this pin to ground to run the regulators in phase (0 phase shift) between sw rising edge of channel 1 and channel 2. tie this pin to intv cc to set 180 phase shift between chan- nels. when this pin is high, the phase shift may also be set by modulating the duty cycle of external clock on the mode/sync pin (channel 1 edge synced to rising edge of external clock, channel 2 edge synced to falling edge of external clock). see applications section for more details. pgood2 (pin 5/pin 6): open drain power good indicator for channel 2. ilim (pin 6/pin 7): current limit select pin. tying this pin to ground sets the full current limit for both channels. tying this pin to intv cc drops the current limit by a factor of 2 for both channels. biasing this pin to 1 v sets the current on channel 1 to be the full amount, and the current on channel 2 to be dropped by a factor of 2. vin2 (pin 7/pin 8): input voltage of channel 2 step-down regulator. may be a different voltage than v in1 . sw2 (pin 8/pin 9): switch node connection to the induc- tor of channel 2 step-down regulator. run 2 ( pin 9/pin 10): logic controlled run input to chan- nel 2. do not leave this pin floating. logic high activates the step-down regulator. fb2 (pin 10/pin 11): feedback input to the error amplifier of channel 2 step- down regulator. connect resistor divider tap to this pin. the output voltage can be adjusted from 0.6v to v in by: v out = 0.6v ? [1 + (r2/r1)]. (figure 2) for fixed v out options, connect the fb pin directly to v out . intv cc (pin 11/pin 12): low dropout regulator. bypass with a low esr capacitor of at least 1f to ground. fb1 (pin 12/pin 13): feedback input to the error amplifier of channel 1 step- down regulator. connect resistor divider tap to this pin. the output voltage can be adjusted from 0.6v to v in by: v out = 0.6v ? [1 + ( r2/r1)]. (figure 2) for fixed v out options, connect the fb pin directly to v out . run1 (pin 13/pin 14): logic controlled run input to channel 1. do not leave this pin floating. logic high acti - vates the step-down regulator. sw1 ( pin 14/pin 16): switch node connection to the inductor of channel 1 step-down regulator. gnd ( pin 15/pin 17): ground for power and signal ground. the exposed pad must be connected to pcb ground for rated electrical and rated thermal performance. sv in (na/pin 2): signal v in pin. this input powers the intv cc . may be a different voltage than either v in1 or v in2 . connect sv in to either v in1 or v in2 , whichever one is higher. for applications where it is not known which v in is higher, connect external diode between sv in to both v in1 and v in2 to ensure that sv in is less than a diode drop from the higher of v in1 or v in2 . (dfn/msop) ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
9 for more information www.linear.com/ltc3622 b lock diagra m ? + + ? + ? + + ? + ? 0.5ms soft-start slope compensation buck logic and gate drive 0.6v fb1 run1 pgood1 mode/sync phase intv cc error amplifier burst comparator main i-comparator overcurrent comparator reverse current comparator ldo oscillator current limit select v in1 sw1 gnd i lim channel 1 channel 2 same as channel 1 3622 bd v in ?5v intv cc sw2 sv in (msop only) clk1 clk2 fb2 run2 pgood2 v in2 fixed v out ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
10 for more information www.linear.com/ltc3622 o pera t ion the ltc3622 is a dual high efficiency monolithic step- down regulator, which uses a constant frequency, peak current mode architecture. it operates through a wide v in range and regulates with ultralow quiescent current. the operation frequency is set at either 2.25 mhz or 1 mhz and can be synchronized to an external oscillator 50% of the inherent frequency. to suit a variety of applications, the selectable mode/sync pin allows the user to trade off output ripple for efficiency. for each channel, the output voltage is set by an external divider returned to the fb pin. an error amplifier compares the divided output voltage with a reference voltage of 0.6v and adjusts the peak inductor current accordingly. overvoltage and undervoltage comparators will pull the pgood output low if the output voltage is not within 7.5% of the programmed value. the pgood output will go high immediately after achieving regulation and will go low 32 clock cycles after falling out of regulation. main control loop during normal operation, the top power switch (p-channel mosfet) is turned on at the beginning of a clock cycle. the inductor current is allowed to ramp up to a peak level. once the level is reached, the top power switch is turned off and the bottom switch ( n-channel mosfet) is turned on until the next clock cycle. the peak current level is con - trolled by the internally compensated i th voltage, which is the output of the error amplifier. this amplifier compares the fb voltage to the 0.6 v internal reference. when the load current increases, the fb voltage decreases slightly below the reference, which causes the error amplifier to increase the i th voltage until the average inductor current matches the new load current. the main control loop is shut down by pulling the run pin to ground. low current operation tw o discontinuous conduction modes ( dcm) are available to control the operation of the ltc3622 at low currents. both modes, burst mode operation and pulse-skipping mode, automatically switch from continuous operation to the selected mode when the load current is low. to optimize efficiency, burst mode operation can be se - lected by tying the mode/sync pin to intv cc . in burst mode operation, the peak inductor current is set to be at least 400 ma, even if the output of the error amplifier de- mands less. thus, when the switcher is on at relatively light output loads, fb voltage will rise and cause the i th voltage to drop. once the i th voltage drops low enough,the switcher goes into sleep mode with both power switches off. the switchers remain in this sleep state until the external load pulls the output voltage below its regulation point. when both channels are in sleep mode, the part draws an ultralow 5a of quiescent current from v in . to minimize v out ripple, pulse-skipping mode can be selected by grounding the mode/sync pin. in ltc3622, pulse-skipping mode is implemented similarly to burst mode operation with the peak inductor current set to be at above 66 ma. this results in lower ripple than in burst mode operation with the trade-off being slightly lower efficiency. high duty cycle/dropout operation when the input supply voltage decreases towards the output voltage, the duty cycle increases and slope compensation is required to maintain the fixed switching frequency. the ltc3622 has internal circuitry to accurately maintain the peak current limit (i lim ) of 1.8 a even at high duty cycles. as the duty cycle approaches 100%, the ltc3622 enters dropout operation. during dropout, the part will transition in and out of sleep mode depending on the output load current. this significantly reduces the quiescent current, thus prolonging the use of the input supply. ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
11 for more information www.linear.com/ltc3622 figure 1. 90 phase shift set by external clock o pera t ion v in overvoltage protection in order to protect the internal power mosfet devices against transient voltage events, the ltc3622 constantly monitors the v in1 and v in2 pins for an overvoltage condi- tion. when v in1 or v in2 rise above 18.5 v, both regulators suspend operation by shutting off both power mosfets. once v in drops below 18.2 v, the regulator immediately resumes normal operation. the regulators execute soft- start when exiting an overvoltage condition. low supply operation the ltc3622 incorporates undervoltage lockout circuits which shut down the part when the input voltages drop below 2.5 v. as the input voltages rise slightly above the undervoltage threshold, the switchers will begin basic op - eration. however , the r ds( on) of the top and bottom switch of each channel will be slightly higher than that specified in the electrical characteristics due to lack of gate drive. refer to graph of r ds(on) versus v in for more details. phase selection the two channels of ltc3622 can operate in phase , 180 out- of- phase ( anti- phase) depending on the state of phase pin- low, or high, respectively. anti-phase generally re - duces input voltage and current ripple. crosstalk between switch nodes sw1, sw2 and components or sensitive lines connected to fbx, can sometimes cause unstable switching waveforms and unexpectedly large input and output voltage ripple. the situation improves if rising and falling edges of the switch nodes are timed carefully not to coincide. depending on the duty cycle of the two channels, choose the phase difference between the channels to keep edges as far away from each other as possible. crosstalk can generally be avoided by carefully choosing the phase shift such that the sw edges do not coincide. however, there are often situations where this is unavoid - able, such as when both channels are operating at near 50% duty cycle. in such cases, the optimized phase shift can be set by modulating the duty cycle of external clock on the mode/sync pin (channel 1 edge synced to rising edge of external clock, channel 2 edge synced to falling edge of external clock), while keeping the phase pin volt - age high. figure 1 shows a 90 phase shifting between two channels. table 1 shows the phase selection by the phase pin. table 1. phase selection no external clk external clk phase = 0 0 phase shift 0 phase shift phase = intv cc 180 phase shift phase shift determined by clock edges soft-start the ltc3622 has a 500 s soft-start ramp for each channel when enabled. during soft-start operation, the switchers operate in pulse-skipping mode. external clock sw1 sw2 3622 f01 500ns/div ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
12 for more information www.linear.com/ltc3622 output voltage programming for non-fixed output voltage parts, the output voltage is set by external resistive dividers according to the follow - ing equation: v out = 0.6v ? 1 + r2 r1 ? ? ? ? ? ? the resistive divider allows the fb pin to sense a fraction of the output voltage as shown in figure 2. for fixed v out parts, tie fb directly to v out , as r2 and r1 are matched internal resistors. a pplica t ions i n f or m a t ion figure 2. setting the output voltage note that ripple current ratings from capacitor manufac- turers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for low input voltage applications, sufficient bulk input capacitance may be needed to minimize transient effects during output load changes. output capacitor (c out ) selection the selection of c out is determined by the effective series resistance ( esr) that is required to minimize voltage ripple and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple , v out , is determined by: v out < i l 1 8 ? ? ? c out + esr ? ? ? ? ? ? the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer and hybrid conductive polymer capacitors are very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is importance to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteristics and small footprints. using ceramic input and output capacitors higher capacitance value, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used v out c ff r2 r1 3622 f02 fb gnd ltc3622 input capacitor (c in ) selection the input capacitance, c in , is needed to filter the square wave current at the drain of the top power mosfet. to prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current should be used. the rms current calculation is different if the part is used in in-phase or out-of-phase. for "in phase", when v out1 = v out2 v out (v in C v out ) v in this formula has a maximum at v in = 2v out . this simple worst case is commonly used to determine the highest i rms . for out-of-phase case, the ripple current can be lower than the " in phase" current. the maximum current typically oc - curs when v out1 C v in /2 = v out2 or when v out2 C v in /2 = v out1 . as a good rule of thumb, the amount of worst case ripple is about 75% of the worst case ripple in the in-phase mode. also note that when v out1 = v out2 = v in /2 and i1 = i2, the input current ripple is at its minimum. ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
13 for more information www.linear.com/ltc3622 a pplica t ions i n f or m a t ion at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the v in input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r and x7r dielectric formulations. these dielectrics have the best temperature and voltage char - acteristics of all the ceramics for a given value and size. since the esr of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. typically, five cycles are required to respond to a load step, but only in the first cycle does the output voltage drop linearly. the output droop, v droop , is usually about three times the linear drop of the first cycle. thus, a good place to start with the output capacitor value is approximately: c out = 3 i out ? o ? v droop more capacitance may be required depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. a 10 f ceramic capacitor is usually enough for these conditions. place this input capacitor as close to the v in1 and v in2 pins as possible. output power good when the ltc3622s output voltages are within the 7.5% window of the regulation point, the output voltages are good and the pgood pins are pulled high with external resistors. otherwise, internal open-drain pull-down devices (275) will pull the pgood pins low. to prevent unwanted pgood glitches during transients or dynamic v out changes, the ltc3622s pgood falling edge includes a blanking delay of approximately 32 switching cycles. frequency synchronization capability the ltc3622 has the capability to synchronize to a 50% range of the internal programmed frequency. it takes several cycles of external clock to engage the sync mode, and roughly 2 s for the part to detect the absence of the external clock signal. once engaged in sync, the ltc3622 immediately runs at the external clock frequency. inductor selection given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: i l = v out ? ? l 1C v out v in(max) ? ? ? ? ? ? ? ? lower ripple current reduces power losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a trade-off between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 50% of i out(max) . to guarantee that ripple current does not exceed a specified maximum, the induc- tance should be chosen according to: l = v out ? ? i l(max) 1C v out v in(max) ? ? ? ? ? ? ? ? once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. as the inductance or frequency in- creases, core loss decreases. unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. ferrite designs have very low core losses and are pre - ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
14 for more information www.linear.com/ltc3622 a pplica t ions i n f or m a t ion ripple current and consequent output voltage ripple. do not allow the core to saturate! different core materials and shapes change the size/cur - rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/emi requirements. new designs for table 2. inductor selection table inductor inductance (h) dcr (m) max current (a) dimensions (mm) height (mm) manufacturer ihlp-1616bz-11 series 1.0 2.2 4.7 24 61 95 4.5 3.25 1.7 4.3 4.7 4.3 4.7 4.3 4.7 2 2 2 vishay www.vishay.com ihlp -2020bz-01 series 1 2.2 3.3 4.7 5.6 6.8 18.9 45.6 79.2 108 113 139 7 4.2 3.3 2.8 2.5 2.4 5.4 5.7 5.4 5.7 5.4 5.7 5.4 5.7 5.4 5.7 5.4 5.7 2 2 2 2 2 2 fdv 0620 series 1 2.2 3.3 4.7 18 37 51 68 5.7 4 3.2 2.8 6.7 7.4 6.7 7.4 6.7 7.4 6.7 7.4 2 2 2 2 toko www.toko.com mplc 0525l series 1 1.5 2.2 16 24 40 6.4 5.2 4.1 6.2 5.4 6.2 5.4 6.2 5.4 2.5 2.5 2.5 nec/t okin www.nec-tokin.com hcm 0703 series 1 1.5 2.2 3.3 4.7 9 14 18 28 37 11 9 8 6 5.5 7 7.4 7 7.4 7 7.4 7 7.4 7 7.4 3 3 3 3 3 cooper bussmann www.cooperbussmann.com rlf 7030 series 1 1.5 2.2 3.3 4.7 6.8 8.8 9.6 12 20 31 45 6.4 6.1 5.4 4.1 3.4 2.8 6.9 7.3 6.9 7.3 6.9 7.3 6.9 7.3 6.9 7.3 6.9 7.3 3.2 3.2 3.2 3.2 3.2 3.2 tdk www.tdk.com we -tpc 4828 series 1.2 1.8 2.2 2.7 3.3 3.9 4.7 17 20 23 27 30 47 52 3.1 2.7 2.5 2.35 2.15 1.72 1.55 4.8 4.8 4.8 4.8 4.8 4.8 4.8 4.8 4.8 4.8 4.8 4.8 4.8 4.8 2.8 2.8 2.8 2.8 2.8 2.8 2.8 w rth elektronik www.we-online.com xfl 4020 series 1.0 1.5 2.2 3.3 4.7 10.8 14.4 21.35 34.8 52.2 8 6.7 6.0 3.9 3.6 4 4 4 4 4 4 4 4 4 4 2 2 2 2 2 coilcraft www.coilcraft.com surface mount inductors are available from toko, vishay, nec/tokin, cooper, tdk and wrth elektronik. refer to table 2 for more details. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to the i load ? esr, where esr is the effective series ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
15 for more information www.linear.com/ltc3622 resistance of c out . i load also begins to charge or dis- charge c out generating a feedback error signal used by the regulator to return v out to its steady state value. during this recovery time, v out can be monitored for overshoot or ringing that indicates a stability problem. the initial output voltage step may not be within the band - width of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. in addition, a feedforward capacitor can be added to improve the high frequency response, shown in figure 2. capacitor c ff provides phase lead by creating a high fre- quency zero with r2, which improves the phase margin. the output voltage settling behavior is related to the stabil- ity of the closed-loop system and demonstrates the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. in some applications, a more severe transient can be caused by switching in loads with large (>1 f) input capacitors. the discharge input capacitors are effectively put in paral - lel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the switch connecting to load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection and soft-starting. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ) where l1, l2 etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in ltc3622 circuit : 1) i 2 r losses, 2) switching and biasing losses, 3) other losses. a pplica t ions i n f or m a t ion 1. i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current flows through inductor l but is chopped between the internal top and bottom power mosfets. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw =(r ds(on)top )(dc)+(r ds(on)bot )(1 C dc) the r ds( on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) 2. the switching current is the sum of the mosfet driver and control currents. the power mosfet driver current results from switching the gate capacitance of the power mosfets. each time a power mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of v in that is typically much larger than the dc control bias current. in continuous mode, i gatechg = f osc (q t + q b ), where q t and q b are the gate charges of the internal top and bottom power mosfets and f osc is the switching frequency. the power loss is thus: switching loss = i gatechg ? v in the gate charge loss is proportional to v in and f osc and thus their effects will be more pronounced at higher supply voltages and higher frequencies. 3. other hidden losses such as transition loss and cop - per trace and internal load resistances can account for additional efficiency degradations in the overall power system. it is very important to include these system level losses in the design of a system. transition loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions. the ltc3622 internal power devices switch quickly enough that these loses are not significant compared to other sources. these losses plus other losses, including diode conduction losses during dead time and inductor core losses, generally account for less than 2% total additional loss. ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
16 for more information www.linear.com/ltc3622 a pplica t ions i n f or m a t ion thermal conditions in a majority of applications, the ltc3622 does not dis- sipate much heat due to its high efficiency. however, in applications where the ltc3622 is running at high ambi- ent temperature , high v in , high switching frequency, and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 160c, all power switches will be turned off until the temperature drops about 15c cooler. to prevent the ltc3622 from exceeding the maximum junction temperature, the user needs to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t rise = p d ? ja as an example, consider the case when the ltc3622 is used in applications where v in = 12 v, i out = i out1 = i out2 = 1 a, ? = 2.25 mhz, v out = v out1 = v out2 = 1.8 v. the equivalent power mosfet resistance r sw is: r sw = r ds(on)top ? v out v in + r ds(on)bot ? 1C v out v in ? ? ? ? ? ? = 370m ? ? 1.8v 12v + 150m ? ? 1C 1.8v 12v ? ? ? ? ? ? = 183m ? the active current through v in at 2.25 mhz without load is about 10 ma, which includes switching and internal biasing current loss, and transition loss. therefore, the total power dissipated by the part is: p d = 2 ? i out 2 ? r sw + v in ? i in(q) = 2 ? 1a 2 ? 183m + 12v ? 10ma = 486mw for the dfn package, the ja is 40 c/w. therefore, the junction temperature of the regulator operating at 25c ambient temperature is approximately: t j = 486mw ? 40c/w + 25c = 44.4c remembering that the above junction temperature is obtained from an r ds(on) at 25 c, we might recalculate the junction temperature based on a higher r ds(on) since it increases with temperature. redoing the calculation assuming that r sw increased 5% at 44.4 c yields a new junction temperature of 45.4 c. if the application calls for a higher ambient temperature and/or higher switching frequency, care should be taken to reduce the temperature rise of the part by using a heat sink or air flow. ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
17 for more information www.linear.com/ltc3622 a pplica t ions i n f or m a t ion v in v in sw1 sw2 l1 l2 gnd gnd c in c in c out2 vias to ground plane vias to ground plane vias to ground plane c out1 36222 f03 figure 3. layout diagram board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3622 ( refer to figure 3). check the following in the layout: 1. do the capacitors c in connect to the v in and gnd as close as possible? these capacitors provide the ac current to the internal power mosfets and their driv - ers. does c vcc connect to intv cc as close as possible? 2. are c out and l closely connected? the (C) plate of c out returns current to gnd and the (C) plate of c in . 3. the resistive divider, r1 and r2, must be connected between the (+) plate of c out and a ground line ter- minated near gnd. the feedback signal v fb should be routed away from noisy components and traces, such as the sw line, and its trace should be minimized. keep r1 and r2 close to the ic. 4. solder the exposed pad (pin 15 for dfn, pin 17 for msop) on the bottom of the package to the gnd plane. connect this gnd plane to other layers with thermal vias to help dissipate heat from the ltc3622. 5. keep sensitive components away from the sw pin. the input capacitor, c in , feedback resistors, and intv cc bypass capacitors should be routed away from the sw trace and the inductor. 6. a ground plane is highly recommended. 7. flood all unused areas on all layers with copper, which reduces the temperature rise of power components. these copper areas should be connected to gnd. ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
18 for more information www.linear.com/ltc3622 a pplica t ions i n f or m a t ion 619k 619k 137k 3622 f04 84.5k 22pf 22pf v in 17v max v out1 5v 1a v out2 3.3v 1a c out1 22f c out2 22f v in1 intv cc mode/sync phase i lim v in2 run1 run2 sw2 sw2 fb2 3.3h 2.7h fb2 gnd pgood1 pgood2 ltc3622-2 c in 10f c1 1f figure 4. 5v/3.3v v out burst mode operation application design example as a design example, consider using the ltc3622 in an application with the following specifications: v in1 = v in1 = 10.8v to 13.2v v out1 = 5v v out2 = 3.3v i out1(max) = 1a i out2(max) = 1a i out(min) = 0 f sw = 2.25mhz because efficiency is important at both high and low load current, burst mode operation will be utilized. given the internal oscillator of 2.25 mhz, we can calculate the inductors value for about 40% ripple current at maxi - mum v in : l1 = 5v 2.25mhz ? 0.4a ? ? ? ? ? ? 1C 5v 13.2v ? ? ? ? ? ? = 3.4h l2 = 3.3v 2.25mhz ? 0.4a ? ? ? ? ? ? 1C 3.3v 13.2v ? ? ? ? ? ? = 2.75h using standard value of 3.3 h and 2.7 h for inductors results in maximum ripple currents of: i l1 = 5v 2.25mhz ? 3.3h 1C 5v 13.2v ? ? ? ? ? ? = 0.42a i l2 = 3.3v 2.25mhz ? 2.7h 1C 3.3v 13.2v ? ? ? ? ? ? = 0.41a c out will be selected based on the esr that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. for this design, a 22f ceramic capacitor will be used. c in should be sized for a maximum current rating of: i rms1 = 1a 5 13.2 ? ? ? ? ? ? 13.2 5 C 1 = 0.49a i rms2 = 1a 3.3 13.2 ? ? ? ? ? ? 13.2 3.3 C 1 = 0.43a decoupling the v in1 and v in2 pins with 10 f ceramic capacitors is adequate for most applications. ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
19 for more information www.linear.com/ltc3622 typical a pplica t ions 5v/3.3v v out , burst mode operation, in-phase switching efficiency vs load load step waveform 619k 619k 137k 3622 ta02 84.5k 22pf 22pf v in 17v max v out1 5v 1a v out2 3.3v 1a c out1 22f c out2 22f v in1 intv cc mode/sync phase i lim v in2 run1 run2 sw1 sw2 fb1 6.8h 3.3h fb2 gnd pgood1 pgood2 ltc3622-2 c in 10f c1 1f load current (a) efficiency (%) 3622 ta02a 90 80 100 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 v out = 3.3v v out = 5v v in = 12v f sw = 2.25mhz burst mode operation i l 500ma/div v out ac-coupled 200mv/div 3622 ta02b v in = 12v v out1 = 5v i load = 5ma 500ma burst mode operation f sw = 2.25mhz 40s/div ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
20 for more information www.linear.com/ltc3622 typical a pplica t ions dual output regulators from multiple input sources 604k 604k 134k 3622 ta06 82.5k 22pf 22pf v in1 12v v out1 5v 1a v out2 3.3v 1a c out1 22f c out2 22f v in1 intv cc mode/sync phase i lim v in2 run1 run2 sw1 sw2 fb1 3.3h 1h fb2 sv in gnd pgood1 pgood2 ltc3622 c in1 10f v in2 5v c in2 10f c1 1f 1f ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
21 for more information www.linear.com/ltc3622 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1.70 0.05 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 45 chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 0.25 0.05 0.50 bsc 3.30 0.05 3.30 0.10 0.50 bsc de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708 rev b) ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
22 for more information www.linear.com/ltc3622 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms16) 0213 rev a 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev a) ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
23 for more information www.linear.com/ltc3622 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 03/15 added ltc3622-23/5 options in header added ltc3622-23/5 to options table added ltc3622-23/5 to electrical characteristics added msop-16e package options added h-grade options clarified pin functions clarified table 2 added msop-16e in #4 all 1 3 1, 2, 3, 22 2, 3, 4 8 14 17 ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa
24 for more information www.linear.com/ltc3622 ? linear technology corporation 2014 lt 0315 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3622 r ela t e d p ar t s typical a pplica t ion 5v/3.3v series output, burst mode operation part number description comments ltc3621/ ltc3621-2 1a, 17v, 1/2.25mhz, synchronous step-down regulator 95% efficiency, v in : 2.7v to 17v, v out(min) = 0.6v, i q = 3.5a, i sd < 1a, 2mm 3mm dfn-6, msop-8e ltc3600 1.5a, 15v, 4mhz synchronous rail-to-rail single resistor step-down regulator 95% efficiency, v in : 4v to 15v, v out(min) = 0v, i q = 700a, i sd < 1a, 3mm 3mm dfn-12, msop-12e packages ltc 3601 15v, 1.5a (i out ) 4mhz synchronous step-down dc/dc converter 95% efficiency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 300a, i sd < 1a, 4mm 4mm qfn-20, msop-16e packages ltc 3603 15v, 2.5a (i out ) 3mhz synchronous step-down dc/dc converter 95% efficiency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 4mm 4mm qfn-20, msop-16e packages ltc 3633a 20v, dual 3a (i out ) 4mhz synchronous step-down dc/dc converter 95% efficiency, v in : 3.6v to 20v, v out(min) = 0.6v, i q = 500a, i sd < 15a, 4mm 5mm qfn-28, tssop-28e packages. a version up to 20v in ltc3605a 20v, 5a (i out ) 4mhz synchronous step-down dc/dc converter 95% efficiency, v in : 4v to 20v, v out(min) = 0.6v, i q = 2ma, i sd < 15a, 4mm 4mm qfn-24 package. a version up to 20v in ltc3604 15v, 2.5a (i out ) 4mhz synchronous step-down dc/dc converter 95% efficiency, v in : 3.6v to 15v, v out(min) = 0.6v, i q = 300a, i sd < 14a, 3mm 3mm qfn-16, msop-16e packages ltc 3624/ ltc3624-2 2a, 17v, 1mhz/2.25mhz synchronous step-down regulator 95% efficiency, v in : 2.7v to 17v, v out(min) = 0.6v, i q = 3.5a, i sd < 1a, 3mm 3mm dfn-8 package 604k 604k 134k 3622 ta03 82.5k 22pf 22pf v in 5v to 17v v out1 5v 1a v out2 3.3v 1a c out1 22f c out2 22f v in1 intv cc mode/sync phase i lim v in2 run1 run2 sw1 sw2 fb1 3.3h 10k 1h fb2 gnd pgood1 pgood2 ltc3622-2 c in 10f c1 1f intv cc ltc 3622/ ltc 3622 -2/ ltc 3622-23/5 3622fa

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